In RISC-V instruction set manual, the shift Immediate instructions:
- SLLI (Shift Left Logical Immediate).
- SRLI (Shift Right Logical Immediate).
- SRAI (Shift Right Arithmetic Immediate).
It is mentioned in the manual
Shifts by a constant are encoded as a specialization of the I-type format. The operand to be shifted is in rs1, and the shift amount is encoded in the lower 5 bits of the I-immediate field. The right shift type is encoded in a high bit of the I-immediate. SLLI is a logical left shift (zeros are shifted into the lower bits); SRLI is a logical right shift (zeros are shifted into the upper bits); and SRAI is an arithmetic right shift (the original sign bit is copied into the vacated upper bits).
When it is said that
shift amount is encoded in the lower 5 bits of the I-immediate field.
How it will be encoded exactly?
Another thing does that mean it will take multiple clock cycles to shift as specified in the lower 5 bits of the I-immediate? or can this be done in one clock cycle?
2 Answers
You can find the answer directly in the RISC-V specifications.
imm[11:5] imm[4:0] rs1 func3 rd opcode inst
------------------------------------------------------------ 0000000 shamt rs1 001 rd 0010011 SLLI 0000000 shamt rs1 101 rd 0010011 SRLI 0100000 shamt rs1 101 rd 0010011 SRAIAs for the latency, the ISA only deals with architectures not micro-architectures.
That means that two RISC-V conforming CPUs can execute a shift in a different number of clock cycles.
Lots of options for doing a shift implementation. The least hardware is to a bit at a time, so 32 cycles for a 32 bit shift. A barrel shifter is much more hardware intensive but can shift 32 bits in about the same time as a 32 add. Note that the add needs to propagate carry bits while the 32 bit barrel shifter needs 5 stages (2^^5 = 32). One trick is to break the shift between stages in a multistage pipelined processor. Do an optional bit reverse, 3 barrel shift stages in the EX (Execute) cycle, then the last 2 barrel shift stages in the MEM (Memory/Load/Store) cycle with an optional bit reverse. Latency is now two cycles for the shift. Early complete logic can be added so two or three bit shifts complete in one cycle. Byte shift logic can also be added to do 8x bit shifts in one cycle. Note the bit reversal allows all shifts SLL,SRL,SRA to be done in one direction, shift right, saving some logic. So, many options in the hardware design, add more hardware logic and shifts can be done very fast!
