JK Flip-flop using D Flip-flop and gate level simulation does not stop

I'm trying to implement a JK flip-flop with a D flip-flop and a gate level, but the problem is that when I run the code, the terminal doesn't show me anything. It's like it has always been calculating but nothing is shown. I need to press crtl + c to stop the process, and this is when cmd shows something, but it is not the complete result. I attached my code and images of the cmd.

module D_flip_flop (input D,clk,Reset,enable,output reg F); always @(*) begin if (Reset) F<='b0; else if (enable && clk) F<=D; end
endmodule
module JK_flip_flop(input J,K,clk,Reset,enable,output Q); wire S1,S2,S3,S4,S5; D_flip_flop D1(S4,clk,Reset,enable,Q); not N2(S5,Q); and A1(S1,J,S5); not N1(S3,K); and A2(S2,S3,Q); or O1(S4,S1,S2);
endmodule

testbench:

module testbench();
reg clk,reset,enable,J,K;
wire Q;
JK_flip_flop J1(J,K,clk,reset,enable,Q);
initial begin $display("\n"); $display("Flip Flop JK"); $display("J K clk Reset Enable | Q "); $display("----------------|---"); $monitor("%b %b %b %b %b | %b", J,K,clk,reset,enable,Q); J=0;K=0;reset=1;enable=0;clk=0; #1 reset=0;enable=1; #10 J=0;K=1; #10 J=1;K=0; #10 J=0;K=1; #10 J=1;K=1; #10 J=0;K=0; #50 $finish;
end
always begin #5 clk =~clk; end initial begin $dumpfile("Ej3_tb.vcd"); $dumpvars(0, testbench);
end
endmodule

Terminal before top the process:

Terminal after stop Process:

The JK flip-flop i'm trying to implement:

I don't know why this happening.

1 Answer

That is an incorrect way to model a DFF in Verilog. This is the recommended way, triggering off the rising edge of the clock:

module D_flip_flop (input D,clk,Reset,enable, output reg F); always @(posedge clk) begin if (Reset) F <= 1'b0; else if (enable) F <= D; end
endmodule

The above code uses a synchronous reset.

This change allows the simulation to terminate cleanly (without a Ctrl-C).