I am trying to implement 4x1 multiplexer in Verilog. I want to connect enable (en) as a port which input '1'(high) can ON the MUX and '0'(low) turn OFF this multiplexer. Please suggest some modifications in my code. Thanks in Advance.
module mux_4_to_1( input d,c,b,a, //Inputs input s1,s0, //Select Lines input en, //enable output reg y //output ); always @ (*) begin case (s0 | s1) 2'b00 : y <= a; 2'b01 : y <= b; 2'b10 : y <= c; 2'b11 : y <= d; default : y <= 0; endcase end endmodule 1 Answer
You want en to act as a global switch to turn on or off the mux, so it gets the highest priority.
always @ (*) begin if (en) begin case ({s0, s1}) // pay attention here 2'b00 : y = a; 2'b01 : y = b; 2'b10 : y = c; 2'b11 : y = d; default : y = 0; endcase end else begin y = 1'b0; // your question didn't specify the expected output when OFF end end Please notice I've changed case (s0 | s1) to case ({s0, s1}).
s0 | s1 returns a 1-bit wide result, while you need the concatenation of s0 and s1.
Also, I replaced all NBA <= by BA =.
And, the default branch actually couldn't happen in silicon because you've specified all possible combinations. But if you think it maybe helpful in simulation, you may leave it.
